DC-DC converters have two basic control mechanisms: voltage and current control. Although the advantages of current-mode control over conventional voltage mode control have often been demonstrated, the typical peak-sensing current mode converter has several drawbacks. Peak-sensing converters usually show inherent open loop instability above 50% duty cycle, a non-ideal loop response, a tendency towards subharmonic oscillation and noise sensitivity when the inductor ripple is small. Most or all of these problems can be reduced or even overcome with a technique referred to as slope compensation.
FIG. 1 shows simplified circuit diagram of a DC-DC step down converter using peak current sensing in a current control mode. There is a power switch S1 (e.g. a NPN bipolar transistor), and inductor L, a diode D, a capacitor C and a load RL. The collector of bipolar transistor S1 is coupled to receive primary input voltage VI, which may be provided by a battery. The emitter of power switch S1 is coupled to a cathode of diode D and inductor L. When S1 is turned on, the inductor current IL through inductor L increases. When power switch S1 is turned off, the inductor current IL is supplied through diode D, but decreases slowly. Capacitor C serves as buffer capacitor. The behavior of inductor current IL is also shown in the small diagram.
There are two control loops, one for the output voltage VO and one for the inductor current IL. VO is compared with a reference voltage VREF in error amplifier AMP which provides an error signal VE. A slope compensation voltage VC is subtracted from VE and the resulting voltage VX is fed to a negative input of comparator COMP. The positive input of comparator COMP receives a voltage VS that is proportional to the inductor current IL. Comparator COMP serves to implement a peak current sensing mechanism. If IL exceeds a maximum value, the output of comparator COMP turns to low. The output of comparator COMP is coupled to the reset input R of an RS latch L1. A logic low level on input R sets the output of latch L1 to low and the power switch S1 is turned off. This provides that IL decreases. An oscillator OSC provides pulses of a period T to set input S of RS-latch L1. A pulse on set input S turns the output of latch L1 to high and the power switch S1 is switched on until both inputs R and S are again low. The current IL increases until VS exceeds VX and S1 is turned off again. The compensation voltage VC provides that VX is drops linearly for a constant VE over period T. The maximum voltage step of VC is A.
FIG. 2 shows two waveforms illustrating the need for slope compensation in general. The inductor current IL, for example IL of the prior art current mode DC-DC converter shown in FIG. 1 without a compensation voltage VC, is shown for two different duty cycles D=TON/TS. In the upper diagram, the duty cycle is smaller than 50% (duty cycle D<0.5). The rising slope mr is therefore steeper than the falling slope mf of the inductor current IL. The solid line IL is the ideal current and the dashed line a more realistic current. Even for a significant initial deviation of the real current IL from the ideal curve, the deviation is damped out over several cycles, i.e. the first deviation ΔI1 is greater than the second deviation ΔI2 which is greater than the third deviation ΔI3. In order to comply with the units of the diagram the deviations may be interpreted as ΔI1*RS, ΔI2*RS, or ΔI3*RS. The diagram below shows the same situation for a duty cycle D greater than 50% (duty cycle>0.5). Here, the falling slope mf is steeper than the rising slope mr. Now the deviation from the ideal curve increases, i.e. ΔI1<ΔI2<Δ3. This situation can lead to instability. For the peak current control step down converter, disturbances of current IL are only damped out for duty cycles below 50%.
FIG. 3 shows the inductor current IL for the circuit shown in FIG. 1 with slope compensation voltage VC. Voltage VX decreases linearly over period TS. This reduces the maximum admissible peak current for inductor current IL. Although the duty cycle is smaller than 50%, the deviation from the ideal curve is damped out. Performing linear slope compensation as shown in FIG. 3 can be regarded as changing rising slopes mr and falling slopes mf of the sensed inductor current. The rising slope is pushed towards greater values (i.e. it is made steeper) and the falling slope is pushed toward lower value (i.e. it is made flatter).
The compensation slope is a function of the input voltage VI, the output voltage VO, and the inductor L. Furthermore, DC-DC converters are operated at several different and even varying operation frequencies. The amount of slope compensation depends on static design choices (frequency FS=1/TS, inductance L of inductor) and varying conditions as VI and the duty cycle D=TON/TS.
Some prior art DC-DC converters select the amount of slope compensation conservatively with regard to worst case system parameters. This is sub-optimal as the converter is driven in voltage mode control which makes outer loop stability problematic and counteracts the benefits of primarily using current mode control. Too large slope compensation values limit the inductor current capability or require an additional mechanism for raising the current limit.
Although slope compensation is theoretically only needed for duty cycles greater 50%, most prior art devices use compensation also below 50% in order to compensate production spread and to ensure signal integrity.